Intel unveils Foveros 3D chip stacking and new 10nm ‘chiplets’
At an Architecture Day event hosted this week, Intel articulated an unusually lucid strategy for its development of future processors, most of which will revolve around fragmenting the various elements of a modern CPU into individual, stackable “chiplets.” Intel’s big goal for late 2019 is to offer products built on what it calls Foveros 3D stacking: an industry-first implementation of stacked processing components inside a chip. We’ve already seen stacked memory; now, Intel is doing something similar with the CPU, allowing its designers to essentially drop in extra processing muscle atop an already assembled chip die. So your on-die memory, power regulation, graphics, and AI processing can all constitute separate chiplets, some of which can be stacked atop one another. The benefits of greater computational density and flexibility are obvious, but this modular approach also helps Intel skirt one of its biggest challenges: building full chips at 10nm scale.
Intel’s previous 10nm road maps have consistently and repeatedly slipped, and there’s good reason to believe that the company faces insurmountable engineering challenges on that project. An October report from SemiAccurate even suggested that Intel has canceled its 10nm plans altogether, though the grand old chipmaker denied the rumor and said it was “making good progress on 10nm.” The two may, in fact, both be true, judging from Intel’s new disclosures. On the way to Foveros, Intel suggests it will do something it calls 2D stacking, which is a separation of the various processor components into smaller chiplets, each of which can be manufactured using a different production node. Thus, Intel could deliver nominally 10nm CPUs, which will nonetheless have various 14nm and 22nm chiplet modules within them (as shown in the graphic below).
It wouldn’t be an Intel announcement without a new microarchitecture codename to memorize, which, in this instance, is called “Sunny Cove.” Sunny Cove will be at the heart of Intel’s next-generation Core and Xeon processors in the latter half of next year, and Intel makes some general promises about it improving latency and allowing more operations to be executed in parallel (thus acting more like a GPU). On the graphics front, Intel’s also got new Gen11 integrated graphics “designed to break the 1 TFLOPS barrier,” which will be part of 2019 “10nm-based” processors. The one thing that apparently hasn’t changed about Intel’s plans is its intent to introduce a discrete graphics processor by 2020.
Multiple important questions remain unanswered. Will Foveros 3D stacking be part of the Sunny Cove generation of chips, or will it be something entirely separate? Should we look for Foveros-stacked chips in phones and tablets as well as the predictable laptops and desktops? We posed these and other queries to Intel’s representatives, but the company would only say that everything “from mobile devices to the data center” will feature Foveros processors over time, starting in the second half of next year. Given Intel’s historical failure with smartphone chips, and the fact we now have foldable tablets and all sorts of other quirky hybrids, it’s most likely that the new processors will be targeted at the same classes of device in which Intel’s business already operates.
It’s readily apparent from today’s announcements that Intel has engaged in a major rethink and reorganization of its chip design strategy and philosophy. That’s no less than should be expected from a company that hired a new chief architect, Raja Koduri, a year ago from archrival AMD. Koduri was a very senior figure at AMD, and he’s evidently taken on a similarly influential role in steering Intel’s future direction.